1. Field of the Invention
The present invention relates to the digital measurement of the phase of an analog signal, and in particular of a substantially sinusoidal variable-frequency signal generated by a read device of an optical disk.
2. Description of the Related Art
FIG. 1 very schematically shows a laser disk or optical disk player. A disk D, on a surface of which is engraved a track Tr, is maintained in rotation around revolution axis O of the disk. Track Tr forms a spiral centered on axis O, formed of a series of alternations of reflecting and non-reflecting areas, respectively RZ and NZ. The track may also form concentric circles according to an embodiment which will not be described hereafter. The length of the alternation of reflecting and non-reflecting areas is variable and enables coding information on the track. The disk reader includes a read head RH arranged to face the engraved surface of the disk. A light source LS located on the read head illuminates a point of track Tr. Read head RH is radially mobile with respect to the disk so that any point of the track can be illuminated. Four photosensitive cells A, B, C, and D are arranged on the head to receive light reflected by the track. When the read head is aligned with the track, the four photosensitive cells generate voltage signals VA, VB, VC, and VD identical in amplitude and phase. The voltage signals substantially follow a sinusoid having its frequency varying along with the length of the halfwaves of reflecting and non-reflecting areas of the track. Frequency F of these signals varies between a maximum frequency Fmax for a minimum length of the halfwaves, and a minimum frequency Fmin for a maximum length of the halfwaves. The analysis of the variations of the frequency of voltage signals VA, VB, VC, and VD enables finding the information coded on track Tr. When, however, the read head is shifted with respect to the track, the photosensitive cells generate voltage signals VA, VB, VC, and VD of different amplitudes and out of phase. The phase shift of the voltage signals is then measured and provided to a means for controlling the radial position of the read head (not shown), which acts to realign the read head on the track. The means for controlling the read head position may be realized in the form of an analog or digital circuit. The case where this control circuit uses a digital measurement of the phase shift of the voltage signals generated by the photosensitive cells is considered hereafter.
FIG. 2 schematically shows a conventional device used to measure the phase PH of a voltage signal V, generated by one of photosensitive cells A, B, C, and D to digitize this phase at the frequency of a clock signal CK. A similar device is provided to measure the phase of the voltage signal generated by the other photosensitive cells. Means not shown enable subtracting the two phases thus measured. A voltage comparator 2 compares signal V and a value Vs substantially equal to the average value of signal V. A phase-locked loop 4 receives clock signal CK and generates sixteen replicas CK0, CK1, . . . CK15 of clock signal CK, mutually shifted by 1/16th of the period of clock signal CK. Sixteen D flip-flops FF0, FF1, . . . FF15, rated by the output of comparator 2, respectively receive as an input one of replicas CK0, CK1, . . . CK15 generated by phase-locked loop 4. A logic block 6 receives the outputs of flip-flops FF0, FF1, . . . FF15 and generates as a response a phase signal PH coded over four bits.
Each time signal V reaches value Vs, comparator 2 rates D flip-flops FF0 to FF15. Each D flip-flop FF0 to FF15 then generates a signal equal to 1 or 0 according to whether the replica CK0 to CK15 that it receives is equal to 0 or 1. Replicas CK0 to CK15 being each shifted by 1/16th of the period of clock signal CK, a logic processing of the signals generated by D flip-flops FF0 to FF15 enables determining, with an accuracy of 1/16th of the period of clock signal CK, at what time after the beginning of a period of clock signal CK signal V has reached value Vs.
Such a device operates satisfactorily, but it requires use of a phase-locked loop or of a like analog structure to generate replicas CK0 to CK15 of clock signal CK. When such a device is realized in the form of an integrated circuit, it may undergo significant modifications for any change in the manufacturing process, which is not desirable. Further, such an analog structure is difficult to test, and it must be evaluated after manufacturing, which is expensive.
To avoid these disadvantages, it appears to be desirable to provide a digital process for measuring the phase of a signal. A digital method consists of sampling the signal of which the phase is desired to be measured and of determining this phase based on the samples so obtained. Conventionally, such a method implies using calculation means or tables which occupy a significant silicon surface area. Algorithms in which the sampled signal is assimilated to a straight line between two consecutive samples may also be used. These algorithms enable making simpler circuits, but it is generally admitted that they require a high sampling rate. The sampling frequency is thus generally chosen to be at least 10 times greater than the frequency of the signal of which the phase is desired to be measured. Now, it is desired to be able to use as small a sampling frequency as possible.